Welcome to FIREQ#
FIREQ stands for FPGA Instrumentation for Readout and Qubit control. It is an RFSoC-based platform for quantum-control experiments designed to be usable also by researchers without specific FPGA or hardware-design expertise.
For supported boards, FIREQ provides a ready-to-use FPGA bitstream together with the corresponding server software and Python client, allowing users to start running experiments without rebuilding or modifying the underlying hardware design.
At the same time, FIREQ remains fully open and extensible: advanced users can modify the HDL firmware, integrate custom IP blocks, and adapt the platform to new control and readout architectures.
FIREQ combines a high-level Python client, a runtime server, and custom HDL firmware into a unified workflow for signal generation, data acquisition, and low-latency experiment orchestration.
FIREQ Architecture at a glance#
High-level FIREQ workflow across client, server, and RFSoC firmware.#
Platform components#
Python-based interface used to define experiments, submit commands, and manage execution.
Backend service running on the target platform, exposing FIREQ functionality to the client.
Low-level hardware implementation responsible for acquisition, generation, triggering, and timing.
Documentation index#
Board setup, SD card preparation, and first experiment execution.
Experiment definitions, plotting, and command reference.
Deployment, hardware API/driver layer, and runtime usage.
FPGA architecture, AXI interfaces, and register mapping.
Publications, repository links, and support channels.