# Interfaces & Bus Architectures

This document describes the primary bus architectures, memory-mapped interfaces, streaming pipelines, and clock domains connecting the Programmable Logic (PL), Processing System (PS), and RF Data Converters across supported hardware platforms.

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## Bus & Memory-Mapped Interfaces

The firmware integrates three distinct AXI4 protocol variants tailored for control, high-throughput bulk memory access, and continuous streaming across custom IP modules.

### 1. AXI4-Lite (Control & Configuration)
* **Supported IPs**: Generator IP, Acquisition IP, and Trigger Generator IP.
* **Purpose**: Primary interface for control registers, acquisition parameters, trigger setups, and status monitoring.
* **Clock Domain**: Operates directly on the **PL Fabric Clock** domain (`HS_axis_aclk` = **583.68 MHz** on ZCU216), enabling deterministic, low-latency control register access within the high-speed DSP logic domain.

### 2. AXI4-Full (Bulk Data & Memory Mapping)
* **Supported IPs**: Generator IP and Trigger Generator IP.
* **Purpose**: High-throughput memory-mapped transfers between PS memory and IP-internal storage:
  * **Generator IP**: Used for loading arbitrary envelope waveforms into internal dual-port Block RAMs (BRAMs).
  * **Trigger Generator IP**: Used for writing sequence delays and trigger events.
* **Clock Domain**: Operates on the **PS AXI Clock** domain (`LS_axis_aclk` = **100 MHz**), isolating memory write operations from the high-frequency DSP datapath.

### 3. AXI4-Stream (High-Speed Data Pipelines)
* **Supported IPs**: All custom IP modules (Generator, Frequency Multiplexer, Acquisition, AXIS Corssbar Matrix) and RF Data Converters.
* **Purpose**: Continuous, point-to-point data streaming across the internal signal processing pipeline and to/from converter interfaces.
* **Clock Domain**: Synchronous to the `HS_axis_aclk`

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## Data Converter Stream Interfaces & Parallelism

### ZCU216 Platform
* **RF-DAC Parallelism**: Configured with **16 samples per clock cycle** (16-way parallelism) per active channel to support the **9.33888 GSPS** sampling rate at the **583.68 MHz** fabric clock ($16 \times 583.68\text{ MHz} = 9.33888\text{ GSPS}$).
* **RF-ADC Parallelism**: Configured with **4 samples per clock cycle** (4-way parallelism) per active channel to match the **2.33472 GSPS** sampling rate at **583.68 MHz** ($4 \times 583.68\text{ MHz} = 2.33472\text{ GSPS}$).

### RFSoC4x2 Platform
* **RF-DAC Parallelism**: Configured with **16 samples per clock cycle** (16-way parallelism) per active channel to support the **9.33888 GSPS** sampling rate at the **583.68 MHz** fabric clock ($16 \times 583.68\text{ MHz} = 9.33888\text{ GSPS}$).
* **RF-ADC Parallelism**: Configured with **8 samples per clock cycle** (8-way parallelism) per active channel to match the **4,66944 GSPS** sampling rate at **583.68 MHz** ($ 8\times 583.68\text{ MHz} = 4,66944\text{ GSPS}$).

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## Clock Configuration & Active Channel Matrix

The clocking layout and stream topologies vary based on the targeted evaluation platform:

### 1. ZCU216 Reference Configuration

* **Active Channels**:
  * **RF-DAC**: DAC 228 (Channels 0 & 1) and DAC 229 (Channel 0).
  * **RF-ADC**: ADC 224 (Channel 0) and ADC 225 (Channel 0).
* **Clock Domains & Frequencies**:
  * **PL Fabric Clock**: **583.68 MHz** (drives AXI4-Lite registers, AXI4-Stream pipelines, and DSP core logic).
  * **PS AXI Clock**: **100 MHz** (drives AXI4-Full memory-mapped transfers for Generator BRAMs and Trigger parameters).
  * **RF Reference Clock**: **491.52 MHz** provided by the CLK104 daughterboard into master tiles **ADC 225** and **DAC 229** (PLL VCO locked at **9338.88 MHz**).
  * **PL Reference Clock**: **122.88 MHz** provided by CLK104 to drive the PL clocking wizards.
  * **Multi-Tile Sync (MTS)**: Driven by a **7.68 MHz** `PL_SYSREF` signal generated by the LMK04828 synthesizer on CLK104 and routed via a differential input buffer to `user_sysref_dac` to synchronize internal tile dividers.

> **Detailed Tile Specifications**: For a complete overview of converter tiles, clock distribution topologies, and physical constraints, see the **[ZCU216 Overlay Documentation](modules/overlay_zcu216.md)**.

### 2. RFSoC4x2 Configuration

* **Active Channels**:
  * **RF-DAC**: DAC 228 (Channel 0) and DAC 230 (Channel 0).
  * **RF-ADC**: ADC 224 (Channel 0) and ADC 226 (Channel 0).
* **Clock Domains & Frequencies**:
  * **PL Fabric Clock**: **583.68 MHz** (drives AXI4-Lite registers, AXI4-Stream pipelines, and DSP core logic).
  * **PS AXI Clock**: **100 MHz** (drives AXI4-Full memory-mapped transfers for Generator BRAMs and Trigger parameters).
  * **RF Reference Clock**: **491.52 MHz** provided by **LMK04828** into master tiles **ADC 224** and **DAC 230** (PLL VCO locked at **9338.88 MHz**).
  * **PL Reference Clock**: **122.88 MHz** provided by **LMK04828** to drive the PL clocking wizards.
* **Multi-Tile Sync (MTS)**: Driven by a **7.68 MHz** `PL_SYSREF` signal generated by the LMK04828 synthesizer and routed via a differential input buffer to `user_sysref_dac` to synchronize internal tile dividers.

> **Detailed Tile Specifications**: For a complete overview of converter tiles, clock distribution topologies, and physical constraints, see the **[RFSoC4x2 Overlay Documentation](modules/overlay4x2.md)**.