# Overview

FIREQ is an FPGA instrumentation platform for readout and qubit control on RFSoC-based systems. The firmware repository contains the HDL, board constraints, IP integration files, and overlay assets required to build and deploy the platform.

The design is organized around a set of hardware modules that work together to acquire ADC samples, generate drive and readout waveforms, coordinate timing through trigger logic, and expose the required AXI interfaces to the processing system.

## Main components

- Acquisition logic for sampling, demodulation, and stream generation
- Signal generation blocks for drive and readout channels
- Trigger generation for experiment timing and sequencing
- Board constraints and overlay support for RFSoC deployment
- Common include files and parametrized project infrastructure

## System characteristics

The firmware is designed around a mixed control/data-plane structure:

- AXI4-Lite is used for register-level control and configuration.
- AXI4-Full is used for larger memory-mapped transactions and high-throughput data movement.
- The data converter interfaces are dimensioned for the selected RFSoC target.
- Multi-tile synchronization is supported where deterministic phase alignment across converter tiles is required.

This overview page provides the entry point for the firmware-side documentation and links to the detailed module pages and build flow.