# Style Guidelines

## Verilog/SystemVerilog

Naming convention:
- module names: camel Case (ex: myModule)
- module instances: Snake Case (ex: my_module)
- file names: same as the module name + extension (ex: myModule.sv)
- signal names: Snake Case
- port signal names: Snake Case + `_` + `i/o` (ex: my_input_i or my_output_o)
  - except for standardized interface signals like axi interface signals
- parameter/localparam: Pascal Case (ex: MyParameter)
  - except for standardized interface parameters
- defined constant: Screaming Snake Case (ex: MY_DEFINED_CONSTANT)

Verilog or SytemVerilog source or header files must also have a header following this format:  
```
// -----------------------------------------------------------------------------
// File       : myModule.extension
// Author     : John Doe
// Date       : YYYY-MM-GG
// Module     : myModule
// Description: Description of my module or of the header file contents.
// -----------------------------------------------------------------------------
```
Remove the `Module` field for header files.