FIREQSoC

class FIREQ_LL_API.FIREQSoC(*args: Any, **kwargs: Any)

Bases: Overlay

Low-level representation of the FIREQ SoC.

Responsibilities: - Load the bitfile. - Initialise RF clocks (optional). - Use FireqParser on the HWH to:

• Bind AXI full/lite interfaces for FIREQ IPs.

• Build lists of Generator/Acquisition/Trigger IPs.

• Discover infrastructure IPs (RF-DC, AXI switch, DMA).

• Build validated hardware specs (sample rates, Nyquist, etc.).

set_logger(new_logger: Logger) → None

Set the logger for this object.

Parameters:

new_logger (logging.Logger) – Logger object to use

syncronize_mts_groups() → None

Sync DAC and ADC tiles.

set_nyquist_zone(tile: int, block_id: int, zone: int) → None

Set the nyquist zone for a certain DAC or ADC.

Parameters:

• tile (int) – FPGA tile number, such as 228, 224, etc.

• block_id (int) – Converter block number, starts at 0

• zone (int) – Nyquist zone, starts at 1

get_ip_frequency(full_ip_name: str, clock_port: str) → float

Get the fabric frequency of an IP.

Parameters:

• full_ip_name (str) – Full name of the IP.

• clock_port (str) – Name of the clock port of the IP.

Returns:

Fabric frequency in MHz.

Return type:

float

reset_all_ip_memory_and_registers() → None

Reset the registers and memory for all FIREQ IPs in the design.

set_adc_autocalibration_status(adc_index: tuple[int, int], freeze: bool = True) → None

Freeze or unfreeze the calibration of all ADCs.

Parameters:

• adc_index (tuple[int, int]) – Index of the ADC to set the calibration status for as (tile, block).

• freeze (bool) – Whether to freeze the calibration, defaults to True