AXIS Crossbar Matrix#

The axisCrossbarMatrixIP provides flexible connectivity between generators and DACs, enabling real-time routing of 256-bit AXI-Stream signals in the clock cycle domain. It manages priority and contention when multiple generators target the same DAC.

Mode of Operation#

  • Channel Gating: Each input channel is validated via tvalid. The 16-bit tuser signal controls routing and activation:

    • MSB (Bit 15): Channel Enable. Set to 0 to activate; 1 to inhibit.

    • Bits [14:0]: Routing Mask. Bit n maps the input to m0n_axis_tdata (e.g., LSB maps to m00, Bit 14 to m14).

  • Priority Logic: A single slave can target multiple DACs by setting multiple bits in the mask. In case of overlap, lower-indexed slaves take priority (e.g., s00 overrides s01).

  • Collision Detection: If multiple active slaves request the same DAC, the system resolves the conflict using the priority rule and flags the contention via the debug_collisions_o output.

Creating the AXIS CROSSBAR MATRIX IP PROJECT#

To generate a copy of the axis crossbar matrix project:

  • create a directory called workspace/ in the root of this repo

  • move to that directory and source the vivado init script

  • open vivado

  • source the crossbar_project.tcl script located in this directory from the vivado tcl console

Set axisCrossbarMatrixIP.v as the top module for synthesis and implementation; otherwise, use tb_axisCrossbarMatrixIP.sv to simulate with Vivado’s AXI VIP masters to send data to the crossbar matrix IP.