FIREQ Overlay For The RF4x2 Board#

In this directory, you can find all files related to the FIREQ overlay, targeted for the RF4x2 Board.
The FIREQ.bit and FIREQ.hwh files are the prepackaged overlay, and can be used with PYNQ to load the hardware on the PL.

Overlay overview#

This high-performance overlay incorporates the following custom IP cores and hardware modules:

  • 1x Trigger Generator IP: Coordinates synchronous execution across drive and readout channels.

  • 2x Generator IPs: Dedicated hardware signal generators for driving control pulses and readout sequences.

  • 2x Acquisition IPs: High-speed data acquisition units for signal processing, accumulation, and decimation.

  • 1x Crossbar Matrix IP: For flexible routing between Generator IPs and DACs.

RF Data Converter Configuration & Active Channels#

All custom IPs run at a unified fabric clock frequency of 583.68 MHz, matching the AXI Stream interface clock required by the Zynq UltraScale+ RF Data Converter IP, which sets the sampling frequency to 9.33888 GSPS for the DAC and 4.66944 GSPS (DAC/2) for the ADC.
This frequency was chosen based on the standard PLL Reference frequency provided to the board. It was also chosen such that the signal requirements on the SYS_REF synchronization signal are met, allowing to place both ADCs and DACs in a multi-tile sincronization group.

Active Hardware Mapping#

  • Active RF-DAC Channels:

    • DAC 228: Channel 0

    • DAC 230: Channel 0

  • Active RF-ADC Channels:

    • ADC 224: Channel 0

    • ADC 226: Channel 0

Although the system can only handle one Qbit, it was generated with two generator and two acquisition IPs for debugging reasons.

Multi-Tile Synchronization (MTS) & Constraints#

To guarantee phase coherence and deterministic alignment across all converter tiles, the Multi-Tile Synchronization (MTS) feature is enabled in accordance with AMD/Xilinx guidelines (PG269).

Physical timing constraints configured in mts_constraints.xdc:

  • PL SYSREF: The user_sysref_dac (and user_sysref_adc) sync signal is driven by the differential input port, carrying the 7.68 MHz periodic pulse generated by the LMK04828 synthesizer.

  • PL Clock: 122.88 MHz PL system reference clock from LMK04828. This configuration ensures that the sysref_in synchronization pulse aligns digital sampling clocks deterministically across active ADC and DAC tiles.

Memory Buffer & DMA Streaming Pipeline#

Each of the two Acquisition IPs features two internal memory buffers:

  1. Raw / Non-decimated Buffer: Stores high-rate raw acquisition samples with a maximum depth of 16k samples.

  2. Accumulated / Decimated Buffer: Stores downsampled and integrated experimental data with a depth of 2k samples.

An AXI Stream Switch multiplexes the 4 available buffer channels (2 buffers \(\times\) 2 Acquisition IPs) into a single high-throughput AXI DMA stream, enabling rapid memory transfers to the host memory space.

Building the project#

If you wish to build the overlay from scratch, you can use the provided tcl script:

  • create a directory called workspace/ in the root of this repo (if not already present)

  • move to that directory and source the vivado init script

  • open vivado

  • source project tcl script in the vivado tcl console:

    source ../rfsoc4x2_overlay/rf4x2_FIREQ_proj.tcl

  • launch synthesis and implementation

  • after implementation, generate the bitstream

  • you can then export the bitstream and save the FIREQ.hwh file

  • rename both .bit and .hwh files so that they have the same name