DSP Wrapper

The dspWrapper module is a SystemVerilog wrapper that utilizes the DSP48E2 primitive in SIMD TWO24 mode. It performs two independent 24-bit arithmetic additions in parallel within a single DSP slice.

Mode of Operation

The module takes two 48-bit input vectors (data_a_i and data_b_i). Each input is internally split into two 24-bit lanes (Low and High).

The operation performs the following parallel additions:

• Low Lane (bits 23:0): computes the sum of the lower 24 bits of both inputs.

• High Lane (bits 47:24): computes the sum of the upper 24 bits of both inputs.

The final 48-bit result is provided on the data_o output bus.

Technical References

For further details on the DSP48E2 architecture and its SIMD capabilities, please refer to the official documentation: UG974 - Vivado Design Suite: UltraScale Architecture Libraries Guide