AXIS Acquisition#

This module is the Custom IP used to acquire the samples from the ADCs.

Communication Interfaces#

This module has one Lite interface which is used to control the acquisition parameters directly from the PS.

It also has 3 AXI stream interfaces:

  • One Slave AXI stream interface with a parallelism of 4 samples per clock cycle to get samples from the ADC.

  • One full speed AXI stream master interface that output demodulated samples at 4 samples per clock cycle.

  • One 1/8 speed AXI stream master interface, which output demodulated and decimated samples at 1 samples per clock cycle.

All master intefaces output samples on 32-bits since each demodulated sample is 16-bit I/Q pairs whereas the slave stream interface takes 16-bit real samples from the ADCs.
The decimated master stream is the result of the full speed decimated stream passed through a low pass FIR filter. The samples are decimated by a factor of 8 and therefore it outputs 1 32-bit sample (16-bit I/Q pair) per clock cycle.
All master interfaces implement the stream tvalid and tlast signals to make any downstream IPs understand when samples are valid, i.e. when samples are being acquired.

Finally, this module has a N-bit (N=TriggerWordWidth, see common_includes/COMMON_INCLUDES.vh) parallel input called external_trigger.
This input is used in combination with the trigger generator to handle the necessary wave generation timing requirements.
Waves can, in fact, either be triggered via the PS using the AXI Lite interface or by the external_trigger input.
The acquisition IP can be set to listen to one of the bits of the trigger input word and will start generating samples when the correct bit goes high.

Mode of Operation#

This acquisition IP uses the sine cosine generator under the dds_gen/ as a free-running, variable frequency and phase local oscillator for demodulation purposes.

Triggers#

The IP will start the acquisition of a wave when triggered. The output master AXI stream intefaces will set their sample valid output signal high to signal that the current samples are to be acquired. This can be used to send the output to a FIFO buffer that will save the values only when tvalid is set high.
The tvalid signal will be high for a max_duration clock cycles before setting the tlast signal high for one clock cycle as per AXI stream requirements.

There are two ways to trigger the acquisition:

  • Manual trigger, via the AXI Lite (register 0, bit 31)

  • External trigger, via the trigger interface. The N-bit input is compared with the trigger mask set using the AXI Lite (see later)

NOTE: external triggers must be single clock cycle pulses otherwise the acquisition IP will be triggered multiple times. A trigger word made up of all zeros is invalid and will not trigger the acquisition IP.

EXAMPLE: if the external trigger word is 0001 and the mask is set as 0100, the acquisition IP will not start. If the trigger word is 0100, the acquisition IP will start. If the trigger word is 0000, the acquisition IP will never trigger even if the trigger mask is equal to 0000, but you can still manually trigger it.

AXI Lite Register Map#

The AXI Lite interface is used to set control parameters and configuration values. All register numbers are given as 32-bit aligned indexes (register #0 is at 0 + axi_lite_start_address, register #1 at 4 + axi_lite_start_address, etc.). Some parameters exceed the 32-bit register width and are mapped across multiple registers using little-endian formatting.

Control Register, register 0:

  • bit 0 to 15: max_duration_o , max duration of a wave

  • bit 16 to 23: time_of_flight_o, delay for acquisition

  • bit 27: decimated_accumulated_selector_o, selects the accumulation or decimation mode

  • bit 28 (RO): tvalid_debug_i

  • bit 29 (RO): tlast_debug_i

  • bit 30 (RO): Done flag (pulse)

  • bit 31 (W/R): manual_trigger_o

Phase Offset, register 1-2:

  • bit 0 to 47: phase offset in RAD, 48-bit unsigned mapped into [0:2pi[.

Phase Increment, register 3-4:

  • bit 0 to 47: frequency in RAD/SAMPLE, 48-bit unsigned mapped into [0:2pi[/SAMPLE.

Trigger Mask, register 5:

  • bit 0 to 14: trigger mask

  • bit 15 to 31: Reserved for future use

Drivers#

To easily operate this IP on PYNQ overlays, drivers are available for download in the FIREQ Tools repository.
Drivers provide a good abstraction layer that will let you set up and use the IP without going into details on the implementation.

Creating the AXI Acquisition IP PROJECT#

To generate a copy of the AXI_Generator_IP project:

  • create a directory called workspace/ in the root of this repo

  • move to that directory and source the vivado init script

  • open vivado

  • go to tools > settings > vivado store > board repository and add the board_files/ directory located in the root of this repo

  • source the create_project.tcl script located in this directory from the vivado tcl console

Simulate the Acquisition IP#

A testbench is provided to simulate the acquisition IP.
Only the internal module is simulated, not the entire IP with the AXI interfaces.

Creating the AXI Acquisition EXAMPLE OVERLAY#

To generate the example overlay for the AXI acquisition IP:

  • create a directory called workspace/ in the root of this repo (if not already present)

  • move to that directory and source the vivado init script

  • open vivado

  • source the project file overlay_example_gen.tcl located in this directory from the vivado tcl console

  • launch synthesis and implementation. Generate bitstream

  • you can then export the bitstream and you can find the hwh file under workspace/AXI_Acquisition_test_overlay/AXI_Acquisition_test_overlay.gen/sources_1/bd/design_1/hw_handoff/

  • rename both bitstream and .hwh files so that they have the same name

  • you can now load the two files on the board and use them as an overlay