FIREQ Overlay For The ZCU216 Board#

In this directory, you can find all files related to the FIREQ overlay, targeted for the ZCU216 Board.

The FIREQ.bit and FIREQ.hwh files are the prepackaged overlay, and can be used with PYNQ to load the hardware on the PL.

Overlay overview#

This high-performance overlay incorporates the following custom IP cores and hardware modules:

1x Trigger Generator IP: Coordinates synchronous execution across drive and readout channels.
2x Generator IPs: Dedicated hardware signal generators for driving control pulses and multiplexed readout sequences.
2x Acquisition IPs: High-speed data acquisition units for signal processing, accumulation, and decimation.
1x Frequency Multiplexer IP: Used on the readout path to combine multiple frequency tones onto a single DAC output.
1x Crossbar Matrix IP: For flexible routing between Generator IPs and DACs.

RF Data Converter Configuration & Active Channels#

All custom IPs run at a unified fabric clock frequency of 583.68 MHz, matching the AXI Stream interface clock required by the Zynq UltraScale+ RF Data Converter IP.

Active Hardware Mapping#

Active RF-DAC Channels:
- DAC 228: Channel 0 & Channel 1
- DAC 229: Channel 0
Active RF-ADC Channels:
- ADC 224: Channel 0
- ADC 225: Channel 0

RF Data Converter Clocking & Tile Settings#

The reference clocks for the RF Data Converter are provided directly by the CLK104 clocking daughterboard. The primary clock signals from CLK104 arrive at the master distribution tiles: ADC Tile 225 and DAC Tile 229. These master tiles distribute the clock internally to adjacent tiles (Tile224, Tile228, and Tile230).

RF-ADC Tiles (Acquisition)#

Tile	Sampling Rate (\(F_s\))	Max \(F_s\)	Reference Clock	PLL Ref Clock	Fabric Clock	Clock Source	Distribute Clock
ADC 224	2.33472 GSPS	2.500 GSPS	2334.720 MHz	—	583.680 MHz	Tile225	Off
ADC 225	2.33472 GSPS	2.500 GSPS	491.520 MHz	245.76 MHz	583.680 MHz	Tile225	PLL Output (Distributor)
ADC 226	2.00000 GSPS	2.500 GSPS	2000.000 MHz	—	0.0 MHz	Tile226	Off
ADC 227	2.00000 GSPS	2.500 GSPS	2000.000 MHz	—	0.0 MHz	Tile227	Off

PLL Summary: ADC 225 VCO is configured at 9338.88 MHz (\(M=4, R=2\), Fb Div \(= 38\)).

RF-DAC Tiles (Signal Generation)#

Tile	Sampling Rate (\(F_s\))	Max \(F_s\)	Reference Clock	PLL Ref Clock	Fabric Clock	Clock Source	Distribute Clock
DAC 228	9.33888 GSPS	10.000 GSPS	9338.880 MHz	—	583.680 MHz	Tile229	Off
DAC 229	9.33888 GSPS	10.000 GSPS	491.520 MHz	245.76 MHz	583.680 MHz	Tile229	PLL Output (Distributor)
DAC 230	9.33888 GSPS	10.000 GSPS	9338.880 MHz	—	0.0 MHz	Tile230	Off
DAC 231	6.40000 GSPS	10.000 GSPS	6400.000 MHz	—	0.0 MHz	Tile231	Off

PLL Summary: DAC 229 VCO is configured at 9338.88 MHz (\(M=1, R=2\), Fb Div \(= 38\)).

Multi-Tile Synchronization (MTS) & Constraints#

To guarantee phase coherence and deterministic alignment across all converter tiles, the Multi-Tile Synchronization (MTS) feature is enabled in accordance with AMD/Xilinx guidelines (PG269).

Physical timing constraints configured in mts_constraints.xdc:

PL SYSREF: The user_sysref_dac (and user_sysref_adc) sync signal is driven by the differential input port, carrying the 7.68 MHz periodic pulse generated by the LMK04828 synthesizer on the CLK104 board.
PL Clock: The 122.88 MHz PL system reference clock from CLK104 enters through a dedicated differential buffer (util_ds_buf). This configuration ensures that the sysref_in synchronization pulse aligns digital sampling clocks deterministically across active ADC and DAC tiles.

Memory Buffer & DMA Streaming Pipeline#

Each of the two Acquisition IPs features two internal memory buffers:

Raw / Non-decimated Buffer: Stores high-rate raw acquisition samples with a maximum depth of 16k samples.
Accumulated / Decimated Buffer: Stores downsampled and integrated experimental data with a depth of 2k samples.

An AXI Stream Switch multiplexes the 4 available buffer channels (2 buffers \(\times\) 2 Acquisition IPs) into a single high-throughput AXI DMA stream, enabling rapid memory transfers to the host memory space.

Building the project#

If you wish to build the overlay from scratch, you can use the provided tcl script:

create a directory called workspace/ in the root of this repo (if not already present)
create a new project from Vivado and select workspace/ as a main directory
from tcl console move to the workspace/ directory
source the block diagram tcl script in the vivado tcl console:
```
source ../zcu216_overlay/zcu216_overlay.tcl
```
launch synthesis and implementation
after implementation, generate the bitstream
you can then export the bitstream and save the zcu216_overlay.hwh file
rename both .bit and .hwh files so that they have the same name