Generator Sequencer#
This module stores wave definitions and outputs a wave for each trigger received.
It is comprised of two basic building blocks:
a wave memory
an address sequencer
Wave Memory#
The wave memory stores up to 170 wave definitions of 6 words each. These wave definitions are stored in a single block memory of depth 1k words.
Since the maximum read word of a block memory is 64 bits (72 actually but 64 makes it easy to write to memory), every word definition is read across 3 clock cycles.
This method allows to use a minimal number of block memories to generate a large output instead of many memories in parallel.
The wave memory is writeable from the write interface using a 32-bit data bus.
The address is byte aligned and can address up to 1k words.
Address Sequencer#
The address sequencer provides a doubleword aligned address that represents the start address of the wave definition.
Effectively, if the start address is 9, then the memory will read 3 doublewords with addresses 9, 10, 11.
Note that not all start addresses are valid start addresses. Only the ones that are 3 doublewords aligned are valid start addresses (such as 0, 3, 6, 9, etc.).
When a trigger is received, a new address is generated and the current address is used to access the wave memory.
There are two possible address sources at this time:
memory mapped FIFO
LFSR
The lfsr_or_fifo input is used to choose between the two. If set, the LFSR is used as the source.
Memory Mapped FIFO#
The memory mapped FIFO is a memory that is written from the memory interface and is accessed sequentially like a FIFO.
A new value, corrisponding to the wave read address, is read at each trigger input.
The read pointer is reset when the experiment_start input is asserted.
Each entry is 9 bit wide and a write operation only uses the lowest 9 bits of the 32-bit data interface. Addresses are byte aligned and has a depth of 4k.
LFSR#
The linear feedback shift register is a 7 bit LFSR with a loadable seed, loaded when the experiment_start input is asserted.
The address is generated by multipling this address by 3, in order to make sure that the generated address (on 9 bits) is 3 doubleword aligned.
The LFSR can be used to generate a random sequence of waves starting from a seed, which is reloaded any time the experiment start signal is asserted.
Since the LFSR is pseudo random, the sequence can be simulated in software to know the waves generated. The seed helps to create different sequences.
IMPORTANT: the LFSR should never be loaded with a seed equal to zero because it’s a stable state.